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| DisplayPort Lane Extender QLx4270-DP The QLx4270-DP is a settable quad receive-side equalizer with extended functionality for DisplayPort applications. The QLx4270-DP compensates for the frequency dependent attenuation of copper cables, allowing operation on ultra-thin 40AWG cable. The small form factor, highly-integrated quad design is ideal for high-density data transmission applications including active copper cable assemblies. Operating on a single 1.2V power supply, the QLx4270-DP enables per channel throughputs of up to 2.7Gb/s. The QLx4270-DP uses current mode logic (CML) inputs/outputs and is packaged in a 4mmx7mm 46 lead QFN. QLx4270-DP Features * Supports data rates up to 2.7Gb/s per lane * Low power (78mW per channel) * Low latency (<500ps) * Four equalizers in a 4mmx7mm QFN package for straight route-through architecture and simplified routing * Each equalizer boost is independently pin selectable and programmable * 1.2V supply voltage Applications * DisplayPort (VESA DisplayPort Standard v1.1a) * DisplayPort adaptors and repeaters Benefits * Thinner gauge cable * Extends cable reach greater than 5x * Improved BER Typical Application Circuit 1.2V 10nF 6.04k 4-Pair Differential 100 Twin-Axial Cable Tx1[P,N] Tx2[P,N] 100pF VDD 0.1F 0.1F EP CP BGREF OUT1[P,N] OUT2[P,N] 0.1F 0.1F Display Port Sink IN1[P,N] IN2[P,N] Rx1[P,N] Rx2[P,N] Display Port Source Twin Ax 0.1F 0.1F QLx4270-DP IN3[P,N] IN4[P,N] OUT3[P,N] OUT4[P,N] GND 0.1F 0.1F Tx3[P,N] Tx4[P,N] Rx3[P,N] Rx4[P,N] < 5m, 40AWG Connector Module March 3, 2010 FN6972.2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009, 2010. All Rights Reserved All other trademarks mentioned are the property of their respective owners. QLx4270-DP Ordering Information PART NUMBER (Note) QLX4270RIQT7 QLX4270RIQSR PART MARKING QLX4270RIQ QLX4270RIQ TEMP. RANGE (C) 0 to +70 0 to +70 PACKAGE (Pb-Free) 46 Ld QFN 7" Prod. Tape & Reel; Qty 1,000 46 Ld QFN 7" Sample Reel; Qty 100 PKG. DWG. # L46.4x7 L46.4x7 NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pin Configuration QLx4270-DP (46 LD QFN) TOP VIEW CP1[A] CP1[B] CP1[C] CP2[B] CP4[B] CP2[C] 38 BGREF 37 OUT1[P] 36 OUT1[N] 35 VDD 34 OUT2[P] 33 OUT2[N] 32 VDD EXPOSED PAD (GND) 31 OUT3[P] 30 OUT3[N] 29 VDD 28 OUT4[P] 27 OUT4[N] 26 IS3 25 IS4 24 GND 16 17 18 19 20 21 22 23 NC NC CP3[A] CP3[B] CP3[C] CP4[A] CP4[C] CP2[A] DT IN1[P] IN1[N] VDD IN2[P] 1 2 3 4 5 IN2[N] 6 VDD 7 IN3[P] 8 IN3[N] 9 VDD 10 IN4[P] 11 IN4[N] 12 IS1 13 IS2 14 GND 15 2 NC 46 45 44 43 42 41 40 39 NC FN6972.2 March 3, 2010 QLx4270-DP Pin Descriptions PIN NAME DT PIN NUMBER 1 DESCRIPTION Detection Threshold. Reference DC CURRENT threshold for input signal power detection. Data output Out[k] is muted when the power of the equalized version of In[k] falls below the threshold. Tie to ground to disable electrical idle preservation and always enable the limiting amplifier. Equalizer 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground is recommended for each of these pins for broad high-frequency noise suppression. Equalizer 2 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. Equalizer 3 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. Equalizer 4 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. Impedance Select 1. CMOS logic input. When the voltage on this pin is LOW, the single-ended input impedance of In1P and In1N each go above 200k and powers down the channel. This can be used to disable some of the channels in case the DisplayPort application has less than four links, in order to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50. Impedance Select 2. CMOS logic input. When the voltage on this pin is LOW, the single-ended input impedance of In1P and In1N each go above 200k and powers down the channel. This can be used to disable some of the channels in case the DisplayPort application has less than four links, in order to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50. Ground No-Connect Control pins for setting equalizer 3. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25k resistor. Control pins for setting equalizer 4. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25k resistor. Impedance Select 4. CMOS logic input. When the voltage on this pin is LOW, the single-ended input impedance of In1P and In1N each go above 200k and powers down the channel. This can be used to disable some of the channels in case the DisplayPort application has less than four links, in order to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50. Impedance Select 3. CMOS logic input. When the voltage on this pin is LOW, the single-ended input impedance of In1P and In1N each go above 200k and powers down the channel. This can be used to disable some of the channels in case the DisplayPort application has less than four links, in order to save power consumption. Otherwise, connect to VDD to hold the input impedance at 50. Equalizer 4 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. Equalizer 3 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. Equalizer 2 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. Equalizer 1 differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 4GHz frequency response is recommended. External bandgap reference resistor. Recommended value of 6.04k 1%. Control pins for setting equalizer 2. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25k resistor. Control pins for setting equalizer 1. CMOS logic inputs. Pins are read as a 3-digit number to set the boost level. A is the MSB, and C is the LSB. Pins are internally pulled down through a 25k resistor. Exposed ground pad. For proper electrical and thermal performance, this pad should be connected to the PCB ground plane. IN1[P,N] VDD IN2[P,N] IN3[P,N] IN4[P,N] IS1 2, 3 4, 7, 10, 29, 32, 35 5, 6 8, 9 11, 12 13 IS2 14 GND NC CP3[A,B,C] CP4[A,B,C] IS4 15, 24 16, 17, 45, 46 18, 19, 20 21, 22, 23 25 IS3 26 OUT4[N,P] OUT3[N,P] OUT2[N,P] OUT1[N,P] BGREF CP2[C,B,A] CP1[C,B,A] Exposed Pad 27, 28 30, 31 33, 34 36, 37 38 39, 40, 41 42, 43, 44 - 3 FN6972.2 March 3, 2010 QLx4270-DP Absolute Maximum Ratings Supply Voltage (VDD to GND) . . . . . . . . . . . . -0.3V to 1.3V Voltage at All Input Pins . . . . . . . . . . . -0.3V to VDD + 0.3V ESD Rating at all pins . . . . . . . . . . . . . . . . . . . . 2kV (HBM) Thermal Information Thermal Resistance (Typical) JA (C/W) Jc (C/W) 46 Ld QFN (Notes 1, 2) . . . . . . . . . 32 2.3 Operating Ambient Temperature Range . . . . . . 0C to +70C Storage Ambient Temperature Range . . . . -55C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . +125C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. Operating Conditions PARAMETER Supply Voltage Operating Ambient Temperature Bit Rate SYMBOL VDD TA NRZ data applied to any channel CONDITION MIN 1.1 0 1.5 TYP 1.2 25 MAX 1.3 70 2.7 UNITS V C Gb/s Control Pin Characteristics VDD = 1.2V, TA = +25C, and VIN = 800mVP-P, unless otherwise noted. PARAMETER `LOW' Resistance State `MID' Resistance State `HIGH' Resistance State Input Current NOTE: 3. If four CP pins are tied together, the resistance values in this table should be divided by four. SYMBOL CP[k] CP[k] CP[k] Current draw on digital pin, i.e., CP[k] CONDITION MIN 0 22.5 500 30 25 TYP MAX 1 27.5 100 UNITS k k k A NOTES 3 3 3 Electrical Characteristics VDD = 1.2V, TA = +25C, and VIN = 800mVP-P, unless otherwise noted. PARAMETER Supply Current IC Input Amplitude Range DC Differential Input Resistance DC Single-Ended Input Resistance Input Return Loss (Differential) Output Amplitude Range Differential Output Impedance Output Return Loss (Differential) Output Return Loss (Common Mode) SDD22 SCC22 SDD11 VOUT SYMBOL IDD VIN Measured differentially at data source before encountering channel loss Measured on input channel IN[k] Measured on input channel IN[k]P or IN[k]N 50MHz to 1.35GHz Measured differentially at OUT[k]P and OUT[k]N with 50 load on both output pins Measured on OUT[k] 50MHz to 1.35GHz 50MHz to 1.35GHz 340 80 40 9 150 80 10 5 550 105 650 120 100 50 CONDITION MIN TYP 260 1380 120 60 MAX UNITS NOTES mA mVP-P dB mVP-P dB dB 5 5 5 4 4 FN6972.2 March 3, 2010 QLx4270-DP Electrical Characteristics VDD = 1.2V, TA = +25C, and VIN = 800mVP-P, unless otherwise noted. (Continued) PARAMETER Output Return Loss (Com. to Diff. Conversion) Output Residual Jitter Output Transition Time Lane-to-Lane Skew Propagation Delay NOTES: 4. After channel loss, differential amplitudes at QLx4270-DP inputs must meet the input voltage range specified in "Absolute Maximum Ratings" on page 4. 5. Temperature = +25C, VDD = 1.2V. 6. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted signal (as measured at the input to the channel). Total jitter (TJ) is DJpp + 14.1 x RJRMS. 7. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent, media-induced loss only. From IN[k] to OUT[k] tr, tf SYMBOL SDC22 CONDITION 50MHz to 1.35GHz MIN 20 TYP MAX UNITS NOTES dB 5 2.7Gb/s; Up to 2m 38AWG standard twin-axial cable (11.5dB loss) 20% to 80% 30 0.15 60 0.2 100 50 500 UI ps ps ps 4, 6, 7 8 8. Rise and fall times measured using a 1GHz clock with a 20ps edge rate. Control Pin Boost Setting The voltages at the CP pins are used to determine the boost level of each channel of QLx4270-DP. For each of the four channels, k, the [A], [B], and [C] control pins (CP[k]) are associated with a 3-bit non binary word. While [A] can take one of two values, `LOW' or `HIGH', [B] and [C] can take one of three different values: `LOW', `MIDDLE', or `HIGH'. This is achieved by changing the value of a resistor connected between VDD and the CP pin, which is internally pulled low with a 25k resistor. Thus, a `HIGH' state is achieved by using a 0 resistor, `MIDDLE' is achieved with a 25k resistor, and `LOW' is achieved with an open resistance. Table 1 defines the mapping from the 3-bit CP word to the 18 out of 32 possible levels available via the serial interface on the Evaluation Board kit. TABLE 1. MAPPING BETWEEN CP-SETTING RESISTOR AND QLx4270-DP BOOST LEVELS RESISTANCE BETWEEN CP PIN AND VDD CP[A] Open Open Open Open Open Open Open Open Open 0 CP[B] Open Open Open 25k 25k 25k 0 0 0 Open CP[C] Open 25k 0 Open 25k 0 Open 25k 0 Open TABLE 1. MAPPING BETWEEN CP-SETTING RESISTOR AND QLx4270-DP BOOST LEVELS (Continued) RESISTANCE BETWEEN CP PIN AND VDD CP[A] 0 0 0 0 0 0 0 0 CP[B] Open Open 25k 25k 25k 0 0 0 CP[C] 25k 0 Open 25k 0 Open 25k 0 SERIAL BOOST LEVEL 17 19 21 23 24 26 28 31 SERIAL BOOST LEVEL 0 2 4 6 8 10 12 14 15 16 If all four channels are to use the same boost level, then a minimum number of board resistors can be realized by tying together like CP[k][A,B,C] pins across all channels k. For instance, all four CP[k][A] pins can be tied to the same resistor running to VDD. Consequently, only three resistors are needed to control the boost of all four channels. If the CP Pins are tied together and the 25k is used, the value changes to a 3.125k resistor because the 25k is divided by 4. Channel Power-Down The IS[k] pin powers down the equalizer channel when pulled low. This feature allows individually to power down unused channels and to minimize power consumption. Example: for DisplayPort applications with 1 or 2 links, the unused channels may be powered down to save power. The current draw for a channel is reduced from 50mA to 3.8mA when powered down. 5 FN6972.2 March 3, 2010 QLx4270-DP About Q:Active(R) Historically, cable manufacturers have relied on thick wire gauge cables to deliver Deep Color images to the monitors and projectors. However, these cables are bulky, unwieldy and esthetically unappealing. To address this, Intersil has developed its groundbreaking Q:ACTIVE(R) product line. By integrating its analog ICs inside DisplayPort cables, Intersil is able to achieve unsurpassed improvements in cable gauges, reach and transmitted image quality. For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6 FN6972.2 March 3, 2010 QLx4270-DP Package Outline Drawing L46.4x7 46 LEAD THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE (TQFN) Rev 0, 9/09 2.80 4.00 A B 6 PIN 1 INDEX AREA 38 39 42X 0.40 46 6 PIN 1 INDEX AREA 1 7.00 5.60 5.50 0.1 Exp. DAP (4X) 0.05 TOP VIEW SIDE VIEW 24 46X 0.20 4 0.10 M C A B 46X 0.40 23 2.50 0.1 Exp. DAP BOTTOM VIEW SEE DETAIL "X" 16 15 0.70 0.05 0.10 C SEATING PLANE 0.05 C SIDE VIEW C C 0.152 REF 5 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" ( 3.80 ) ( 2.50) NOTES: 1. 2. ( 6.80 ) ( 5.50 ) ( 42X 0.40) 3. 4. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. Unless otherwise specified, tolerance : Decimal 0.05 Dimension applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. (46X 0.20) 6. Tiebar shown (if present) is a non-functional feature. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. ( 46 X 0.60) TYPICAL RECOMMENDED LAND PATTERN 7 FN6972.2 March 3, 2010 |
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